1. Field of the Invention
This invention generally relates to integrated circuit fabrication and, more particularly, to a strained-silicon (Si) channel CMOS device that has shallow trench isolation (STI) regions formed with an oxide liner.
2. Description of the Related Art
In the process of trenching for a STI region, damage can occur in the exposed silicon-containing layers. A STI liner oxidation process is typically carried out at 800–1000 degrees C., growing a 100–300 Å thick layer of SiO2. This oxidation process cures the damaged Si, rounding the STI top and bottom corners and reducing the stress at trench corners. The Si curing induced by this STI liner oxidation step can reduce the device junction leakage up to several orders of magnitude.
For strained-Si channel complementary metal gate over oxide over silicon (CMOS) field effect transistor (FET) processes, the thin layer of strained-Si is deposited on a layer of relaxed silicon germanium (SiGe). Then, the above-described oxidation process can lead to other problems. The exposure of SiGe, in the trenching process and the oxidation ambient environment as the liner oxide is grown, generally results in Ge precipitation into the SiO2 matrix. This Ge precipitation degrades the device performance with respect to junction leakage and device reliability.
It would be advantageous if an oxidation curing process could be performed after a STI trenching, when SiGe layers are etching.
It would be advantageous if a procedure could be developed that prevented the precipitation of Ge, from a SiGe layer, in the oxidation curing of a STI trench.
It would be advantageous if the above-mentioned procedure could be performed using primarily conventional procedures.